Evolution of the Digital Circuits with Variable Layouts
نویسندگان
چکیده
We use evolutionary search to design combinational logic circuits which is based on evolving the functionality and connectivity of a rectangular array of logic cells in addition to the layout of this array. The evolutionary process contains two main steps. Initially the genome fitness in given by the percentage of output bits, which are correct. Once 100% functional circuits have been evolved, the number of gates actually used in the circuit is taken into account in the fitness function. This allows us to evolve circuit with 100% functionality and minimise the number of active gates in circuit structure. 1 PROBLEM DESCRIPTION The choice of suitable circuit layout is very complicated task and is intimately linked the complexity of function implemented (Kalganova, 1998). So, we have tried to solve this problem by evolving the circuit layout at the same time as trying to evolve 100% functional circuits. There are two aspects required to define any combinational logic network. The first is the cell-level functionality and the second is the inter-connectivity of the cells between the circuit inputs and outputs. An encoding of the chromosome was adopted that satisfies these two aspects. A combinational circuit is represented as a rectangular array of logic gates. Each logic cell in this array is uncommitted and can be removed from the network if they prove to be redundant. The inputs of the combinational network such as logical constants, primary and inverted inputs, as well as the outputs of logic cells are labelled with an individual integer. We define each logic function to be chosen from the set of functions AND, OR, NOT, EXOR and multiplexer with primary and inverted inputs. Each input of a logic gate may be connected to the output of a logic gate provided it is to the left of the cell, a logical constant, a primary input or an inverted primary input. The chromosome is represented by a 3-level structure: 1) Layout structure; 2) Circuit structure; 3) Gate (cell) structure. On the first level the global characteristics of the circuit are defined. There are levels-back parameter and the number of rows and columns. On the second level the array of cells are created and the circuit outputs are determined. Finally the third level represents the structure of each cell in the circuit. The data describing the cell contains the number of inputs, the array of inputs and the functional gene. The number of inputs in the cell depends on the type of cell and is defined when the value of functional gene is known.
منابع مشابه
Design and Test of New Robust QCA Sequential Circuits
One of the several promising new technologies for computing at nano-scale is quantum-dot cellular automata (QCA). In this paper, new designs for different QCA sequential circuits are presented. Using an efficient QCA D flip-flop (DFF) architecture, a 5-bit counter, a novel single edge generator (SEG) and a divide-by-2 counter are implemented. Also, some types of oscillators, a new edge-t...
متن کاملStatic Simulation of CNTFET-based Digital Circuits
In this paper we implement a simple DC model for CNTFETs already proposed by us in order to carry out static analysis of basic digital circuits. To verify the validity of the obtained results, they are compared with those of Wong model, resulting in good agreement, but obtaining a lighter ensuring compile and shorter execution time, which are the main character...
متن کاملModeling and Simulation of Substrate Noise in Mixed-Signal Circuits Applied to a Special VCO
The mixed-signal circuits with both analog and digital blocks on a single chip have wide applications in communication and RF circuits. Integrating these two blocks can cause serious problems especially in applications requiring fast digital circuits and high performance analog blocks. Fast switching in digital blocks generates a noise which can be introduced to analog circuits by the common su...
متن کاملModeling of Signals in Subnanosecond Analog-to-Digital Information Converters
The mathematical model and methods of calculation of the layout structure of comparator signal circuits with distributed parameters are presented. The algorithm of computer formulation and solving of equations of transfer functions of comparator circuits is provided. Theoretical substantiation of optimizing the micro-layout of large-scale integration circuits of parallel subnanosecond analog-to...
متن کاملDynamic Simulation of CNTFET-Based Digital Circuits
In this paper we propose a simulation study to carry out dynamic analysis of CNTFET-based digital circuit, introducing in the semi-empirical compact model for CNTFETs, already proposed by us, both the quantum capacitance effects and the sub-threshold currents. To verify the validity of the obtained results, a comparison with Wong model was carried out. Our mode...
متن کاملMOCA ARM: Analog Reliability Measurement based on Monte Carlo Analysis
Due to the expected increase of defects in circuits based on deep submicron technologies, reliability has become an important design criterion. Although different approaches have been developed to estimate reliability in digital circuits and some measuring concepts have been separately presented to reveal the quality of analog circuit reliability in the literature, there is a gap to estimate re...
متن کامل